Browse Prior Art Database

Scheme for Probing Chip Nets in a Multi-Chip Module With Low Net Distortion

IP.com Disclosure Number: IPCOM000099338D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 111K

Publishing Venue

IBM

Related People

Edwards, DL: AUTHOR [+3]

Abstract

Disclosed is a scheme for high performance probing of chip nets on multi-chip modules, from the pin side of the module, at full system speed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Scheme for Probing Chip Nets in a Multi-Chip Module With Low Net Distortion

       Disclosed is a scheme for high performance probing of chip
nets on multi-chip modules, from the pin side of the module, at full
system speed.

      This invention provides a means of monitoring circuit
performance on the substrate top surface of capped modules, from the
back of the module.  The monitoring is at system speeds, without
introducing distortion due to capacitive loading associated with
probes or long parasitic wires. Short wires are used to connect the
probe point to a fixed resistor with the other end terminated at an
unused module I/O (Input/Output).  The high resistance path
(typically, 450 ohms) may be designed into the substrate or
implemented by a discrete "chip resistor".  Alternatively, a chip
common to all multi-chip modules, such as the clock powering quadrant
chip, could be modified to add one or more fixed value resistors for
this function.

      The selected resistance value of 450 ohms, for example, forms a
10:1 divider when terminated by a 50-ohm measurement system.  Other
resistances and systems are well-known to those in the art.
Resistance as high as 1950 ohms (40:1) is common.  By connecting the
net to spare module I/O, the net may be probed from the back of the
substrate by conventional means.  Because the electrical path to the
back of the substrate has high resistance, the net is not disturbed,
and the net can be monitored at full system speeds.

      The high resistance path in the substrate may be designed in
several ways.  One approach would be to design the resistor as an
integral part of the surface metallurgy. For this arrangement, one
discrete wire would connect the selected net to one end of the
"resistor" and a second wire would connect the other end of the
"resistor" to spare EC (Engineering Change) pads that are connected
to module I/O. The top surface resistor may be applied in an unused
area (for example, in the space beyond the last row or column of
chips and the seal area).  Resistive pastes and ohmic contacts are
commonly used in thick film applications, and may be used here.  See
Fig. 1 for this method.

      A second alternative would be to use discrete chip res...