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Generalized Logic Image Masterslice Chip

IP.com Disclosure Number: IPCOM000099342D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 107K

Publishing Venue

IBM

Related People

Hickson Jr, JB: AUTHOR [+3]

Abstract

Disclosed are the arrangements of circuits, interconnecting wires, and power and ground buses on a CMOS masterslice chip. All early manufacturing steps are performed with a standard set of masks, reducing manufacturing costs. Metal and contact layers are patterned last, resulting in a chip with a particular function. Design procedures are relatively simple, and there is minimal time between design completion and chip availability.

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This is the abbreviated version, containing approximately 52% of the total text.

Generalized Logic Image Masterslice Chip

       Disclosed are the arrangements of circuits,
interconnecting wires, and power and ground buses on a CMOS
masterslice chip.  All early manufacturing steps are performed with a
standard set of masks, reducing manufacturing costs.  Metal and
contact layers are patterned last, resulting in a chip with a
particular function.  Design procedures are relatively simple, and
there is minimal time between design completion and chip
availability.

      Around the perimeter of the chip are off-chip driver and
receiver circuits.  Then center region of the chip has an array of
CMOS logic circuits.  Power and ground are supplied to circuits in
each row by buses on M1 (the first metal level).  All M1 buses are
supplied from perpendicular buses on M2 (the second metal level).

      The figure shows a portions of one row of the masterslice.
Buses 1, 2 and diffusions 3, 4 extend horizontally in continuous
bands, crossed by vertical polysilicon strips.  Short poly strips 6
which cross only one part of the row are often connected to buses to
separate circuits.  Longer poly strips 5 are used for transistor
gates.  All stop short of row edges to avoid connecting poly strips
in adjacent rows.  Where poly crosses diffusion, forming a gate, its
width is determined by transistor ground rules, and elsewhere its
width is appropriate for placing contacts to M1.  Devices are
connected to create useful circuits by a combination of contacts
between diffusions and M1, short horizontal M1 wires, contact between
M1 and M2, and short vertical M2 wires.

      Four ad...