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Process for Self-Aligned Common Two-Gate, Six-Transistor, Complementary Metal Oxide Silicon Static Random-Access Memory

IP.com Disclosure Number: IPCOM000099355D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Geipel, H: AUTHOR [+3]

Abstract

A high-density, stable, low-power static random-access memory (SRAM) having high immunity to soft errors can be constructed using the process and structure described. Internal wiring is eliminated by using gate electrodes of NMOS devices as source and drain for PMOS devices and vice versa.

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Process for Self-Aligned Common Two-Gate, Six-Transistor, Complementary Metal Oxide Silicon Static Random-Access Memory

       A high-density, stable, low-power static random-access
memory (SRAM) having high immunity to soft errors can be constructed
using the process and structure described. Internal wiring is
eliminated by using gate electrodes of NMOS devices as source and
drain for PMOS devices and vice versa.

      Referring to the plan view of Fig. 1 and cross section A-A of
Fig.  2, isolation oxide 10 is formed on substrate 12, channel 14 is
implanted, and then gate dielectric 16 is formed.  Then buried
contacts 18, which make direct contact with NMOS gate electrode
material over a diffusion area, are defined and formed and may have
titanium nitride (TiN) plus titanium disilicide (TiSi2) contact
metallurgy applied.

      Referring next to the plan view of Fig. 3 and cross section A-A
of Fig. 4, P+ polysilicon 20 and insulating film 22 are deposited and
defined.  Insulating sidewall spacers 24 are formed by standard
conformal deposition followed by anisotropic etching.  Then, N+
regions 26 are defined and implanted.

      Referring now to the plan view of Fig. 5 and cross section A-A
of Fig. 6, spacers 24 are etched away and P- polysilicon 28 is
deposited and defined. Channel implantation and anneal are applied to
form two PMOS devices in regions 30 using N+ diffusions as gate
electrodes and P+ regions as source and drain.  At the same time, t...