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Pulse-Width Modulated Digital-to-Analog Converter for Dasd Voice Coil Motor

IP.com Disclosure Number: IPCOM000099365D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

DeRemer, RL: AUTHOR [+4]

Abstract

Described is a pulse-width modulate (PWM) digital-to-analog converter (DAC) which is split into digital and analog portions. The digital portion generates a PWM logic signal which is sent to the analog portion. The analog portion receives the PWM logic signal, synchronizes the signal to eliminate delay errors, and then integrates and filters the signal. By splitting the PWM DAC into digital and analog portions, a complex, expensive silicon process is eliminated. An interface between the digital and analog portions requires only a PWM logic signal and a sign signal; therefore, the number of pins on the logic module is reduced. For an 8-bit DAC the number of signals between the logic portion and the analog portion is reduced from 8 to 2.

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Pulse-Width Modulated Digital-to-Analog Converter for Dasd Voice Coil Motor

       Described is a pulse-width modulate (PWM)
digital-to-analog converter (DAC) which is split into digital and
analog portions.  The digital portion generates a PWM logic signal
which is sent to the analog portion.  The analog portion receives the
PWM logic signal, synchronizes the signal to eliminate delay errors,
and then integrates and filters the signal.  By splitting the PWM DAC
into digital and analog portions, a complex, expensive silicon
process is eliminated.  An interface between the digital and analog
portions requires only a PWM logic signal and a sign signal;
therefore, the number of pins on the logic module is reduced.  For an
8-bit DAC the number of signals between the logic portion and the
analog portion is reduced from 8 to 2.

      Refer to Fig. 1 for the following description.  The 8-bit
digital input is made up of D8, D7, D6, D5, D4, D3, D2, D1, with
D8 the most significant bit (MSB) and D1 the least significant bit
(LSB).  D8 is used as the sign bit. The remaining 7 bits are used to
control the PWM logic signal.  A 7-bit binary counter supplies
signals used to generate the PWM timings.  The counter bits are C7,
C6, C5, C4, C3, C2 and C1 with C7 the MSB and C1 the LSB.
For a digital value of 01000000 a signal with a 50 percent duty cycle
at the highest frequency is desired.  All of the bits of the counter
have a 50 percent duty cycle; however, C1 is the highest frequency.
By using C1 rather than C7, the frequency of the signal is 128 times
higher, and a ripple of the PWM DAC output is reduced to 1/128 of the
ripple if C7 is used.
    The logic expression for an algorithm is:
    PWM = D7*C1
    + D6*-C1*C2
    + D5*-C1*-C2*C3
    + D4*-C1*-C2*-C3*C4
    + D3*-C1*-C2*-C3*-C4*C5
    + D2*-C1*-C2*-C3*-C4*-C5*C6
    + D1*-C1*-C2*-C3*-C4*-C5*-C6*C7.
    Fig. 2 illustrates the output PWM pattern for a...