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Combining Memory Operations for Parallel Processors

IP.com Disclosure Number: IPCOM000099368D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Green Jr, PE: AUTHOR [+4]

Abstract

This article describe a means for using a reducing operations on an interconnection bus in a parallel computing network. The idea is to combine operations when possible in order to eliminate bus cycles. To deal with so-called "hot spot" traffic that sometimes occurs in parallel processing systems, several ideas have been proposed for combining operations in multilevel switching networks [1]. A scheme for a bus network that eliminates some operations is proposed in (2). The method described here extends the method of (2) to a large class of combinable operations.

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Combining Memory Operations for Parallel Processors

       This article describe a means for using a reducing
operations on an interconnection bus in a parallel computing network.
 The idea is to combine operations when possible in order to
eliminate bus cycles.  To deal with so-called "hot spot" traffic that
sometimes occurs in parallel processing systems, several ideas have
been proposed for combining operations in multilevel switching
networks [1].  A scheme for a bus network that eliminates some
operations is proposed in (2).  The method described here extends the
method of (2) to a large class of combinable operations.

      More specifically, the following memory operations are
considered:  Read, Write, and an atomic Read-Modify-Write. For a
variable A we denote these operations, respectively by R(A), W(A,B)
and RMW(A,B) where in the case of W, A is the address and B is
the value to be written, and in the case of RMW, A is the address
of the variable read, and B is the new value to be written.  The case
of a collision to the save variable A is denoted by ordered pair
operations where the first operations corresponds to the winner and
the second to a loser as, for example, (W(A,B),R(A)).  Note that
there is one such pair for each loser.  Note also that a processor
may wish to establish connection with a memory sometime during Step 4
above.  Such a processor may not actually participate in Step 4's
contention resolution algorithm, but for our purposes, it can...