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Dense CMOS Ex-or And Ex-nor Circuits

IP.com Disclosure Number: IPCOM000099370D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Brennan, TC: AUTHOR

Abstract

Described is a four-transistor CMOS implementation of the EX-OR and EX-NOR circuits. This is denser than the standard CMPHILO implementation of ten transistors and later designs using seven transistors (*). However, since CMOS designs have images of pairs of PMOS and NMOS transistors, the seven-transistor design would use an area of eight transistors. Note, however, that there is no buffering of the input signal which must be taken into consideration in terms of speed. Also, true and complement inputs are required.

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Dense CMOS Ex-or And Ex-nor Circuits

       Described is a four-transistor CMOS implementation of the
EX-OR and EX-NOR circuits.  This is denser than the standard CMPHILO
implementation of ten transistors and later designs using seven
transistors (*).  However, since CMOS designs have images of pairs of
PMOS and NMOS transistors, the seven-transistor design would use an
area of eight transistors.  Note, however, that there is no buffering
of the input signal which must be taken into consideration in terms
of speed.  Also, true and complement inputs are required.

      In operation, the input signal B selects which transfer
transistors are on, thereby "selecting" which signal, A or the
inverse of A, will appear at the output.  For example, in the EX-OR
circuit a high level for B (1 state) will cause the inverse of signal
A to appear at the output, passing through transistor pair PP2.
Conversely, a low level for B (0 state) will cause the A signal to
appear at the output, passing through transistor pair PP1.  Again,
this is a pass transistor network and there are no bias voltages used
such as Vdd and ground as in normal circuits. The EX-NOR circuit
operates in a very similar manner. Reference (*)  "CMOS Transfer Gate
Exclusive OR Circuit," IBM
     Technical
     Disclosure Bulletin 28, 4303-4304 (March 1986).