Browse Prior Art Database

Improved Self-timed Restore Scheme for Cmos/Bifet Memories

IP.com Disclosure Number: IPCOM000099390D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+3]

Abstract

The following describes an improved self-timed restore scheme which uses the actual internal timing circuits of the array macro to guarantee the best possible cycle times. This technique can be applied to a RAM, a ROS or to any algorithmically generated macro.

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This is the abbreviated version, containing approximately 71% of the total text.

Improved Self-timed Restore Scheme for Cmos/Bifet Memories

       The following describes an improved self-timed restore
scheme which uses the actual internal timing circuits of the array
macro to guarantee the best possible cycle times. This technique can
be applied to a RAM, a ROS or to any algorithmically generated macro.

      A typical self-time scheme (Fig. 1) uses a series of inverter
delays to represent the worst-case access time. This allows the
design to begin restoring the internal signals (wordlines, bitlines,
etc.)  immediately after the access is completed.  Unfortunately, the
delay chain must be greater than the worst-case access time to
account for mismatches in tracking between the inverters and the
actual circuits performing the access.  In addition, the next access
cycle cannot occur until the delay chain has had a chance to reset
itself.  These two conditions lead to a loss in overall cycle time.

      Fig. 2 shows the circuit diagram of the Improved Self-Timed
Restore Scheme.  High performance array applications make use of a
dummy word line (DWL) for optimum clocking for the data-sensing
circuits.  The invention makes use of this signal to trigger the
self-timed restore circuit.

      Initially C0 and DWL are low.  With C0 low, node A is low and
node B is high via devices 1, 2 and 5.  When C0 switches high, C0'
switches high and triggers an access to the memory. During the
access, DWL will go high.  Node A is pulled high an...