Browse Prior Art Database

Switching Noise Minimization Technique

IP.com Disclosure Number: IPCOM000099392D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR [+2]

Abstract

A method is described for providing a switching stagger for noise minimization within an integrated circuit chip. This technique uses an on-chip "regulator circuit" which activates a preset stagger when the individual chip is determined to be a high switching noise part (i.e., fast part of the chip product distribution). The slow or low noise switching distribution of parts bypasses this stagger.

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This is the abbreviated version, containing approximately 64% of the total text.

Switching Noise Minimization Technique

       A method is described for providing a switching stagger
for noise minimization within an integrated circuit chip.  This
technique uses an on-chip "regulator circuit" which activates a
preset stagger when the individual chip is determined to be a high
switching noise part (i.e., fast part of the chip product
distribution).  The slow or low noise switching distribution of parts
bypasses this stagger.

      Under conventional practice, switching staggers have been used
across the completed product distribution without discriminating
against the individual integrated circuit (IC) chip characteristics.
When circuit tolerances are applied, this prior use of stagger
extends the cycle times for the slower distribution of parts which do
not require stagger for switching noise.  This selective use of
stagger across the IC chip enables a faster cycle time without
switching noise problems.

      Figs. 1 and 2 depict a logical implementation of this
"regulator circuit."  Fig. 1 shows a clock pulse (C) to a receiver or
powering circuit which distributes C1 to the inputs of various
delays.  These delays are made up of logic stages implemented on the
same chip with "delay 2" longer than "delay 1" and "delay 3" longer
than "delay 2," etc.  These delayed clock pulse are fed into the
adjoining logic which selects a set of delayed clocks ("fast chip")
or the non-delayed clock in the case of the "slow chip."  Selection
determin...