Browse Prior Art Database

Error Detection for an Instruction Cache/Buffer That is Transparent to The User

IP.com Disclosure Number: IPCOM000099406D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Christiansen, RA: AUTHOR [+2]

Abstract

This article describes a technique for use in a computer system which provides reliability, availability and serviceability (RAS) to an end user.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Error Detection for an Instruction Cache/Buffer That is Transparent to The User

       This article describes a technique for use in a computer
system which provides reliability, availability and serviceability
(RAS) to an end user.

      When a system has an instruction cache/buffer, it is
transparent to the end user.  The only detection presently available
is by some means to detect that the performance has been degraded,
since the system is always going to backing storage, such as
random-access memory (RAM), and never to the cache/buffer.  By adding
a miss detection counter to the logic it can be detected that an
abnormal number of misses has occurred before a hit and an error
condition is flagged.  It can keep running in degraded mode but the
end user can now schedule a part change and is aware of the error.

      Referring to the drawing which is a flow chart of the disclosed
technique, the normal instruction cache/buffer design never has two
misses in a row since, with most straight line coding, when running
out of the buffer, the next several instructions (depending on the
design) or next large block of instruction is fetched.  After the
first miss, the next instruction will be right behind the missed
instruction and fill the cache/buffer for the next instruction
request.  Even with many branch or jump instructions, there should
never be eight misses in a row before a hit is received.  So, if the
number of misses is counted and overflow, say, at...