Browse Prior Art Database

Summing Detector

IP.com Disclosure Number: IPCOM000099410D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR

Abstract

A method is proposed for providing a way to eliminate the effects of false signals by sampling and summing over the entire data valid interval to determine the presence of data. Additionally, this tech- nique makes it possible to trade off the technology requirements of the different elements of the interface between memory array support logic and the system.

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Summing Detector

       A method is proposed for providing a way to eliminate the
effects of false signals by sampling and summing over the entire data
valid interval to determine the presence of data.  Additionally, this
tech- nique makes it possible to trade off the technology
requirements of the different elements of the interface between
memory array support logic and the system.

      With conventional interfacing between memory systems, the
trans- mission paths are matched point to point nets. This requires
that the module, connector, and board paths each must have the same
transmission characteristics.  This proposal provides a way to
operate at high data rates with relaxed transmission characteristics.
 An up/down counter and a detector network are added to each
interface net which samples and sums the level of the data during
transmission with an output based upon the majority level during
transmission.

      Fig. 1 depicts a data transmission interval with various slots
for sampling.  Fig. 2 is an example of a less than perfect data
signal with noise or reflection couplings. The configuration shown in
Fig. 4, consisting of an up/down counter and detection logic, is the
structure SUMMING of this proposal.  The up/down counter is clocked
by an internal on-chip clock with the outputs of the stages of the
counter fed into a logic network which generates set and reset
controls for an output latch.  Fig. 3 describes the logic operation
of the "Summi...