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CACHE Multi-port Output Read Performance Optimization Using Capacitance Isolation

IP.com Disclosure Number: IPCOM000099430D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 5 page(s) / 167K

Publishing Venue

IBM

Related People

Correale, A: AUTHOR

Abstract

This article describes a device and technique wherein the performance of a CACHE memory with at least 2 read ports can be improved by determining when the read addresses are equal and providing capacitive load isolation. Since the overall read performance of the CACHE is limited to the worst-case scenario, the multi-port read operation from a common location limited the performance.

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CACHE

Multi-port

Output Read Performance Optimization Using Capacitance Isolation

       This article describes a device and technique wherein the
performance of a CACHE memory with at least 2 read ports can be
improved by determining when the read addresses are equal and
providing capacitive load isolation.  Since the overall read
performance of the CACHE is limited to the worst-case scenario, the
multi-port read operation from a common location limited the
performance.

      L3 latch arrangements have been extensively utilized to
implement small CACHE memories.  Some implementations required
multiple read ports.  When the address for each read port was the
same, the L3 latch being selected was required to drive all ports
concurrently. This resulted in performance degradation as the
capacitance associated with the read operation was a function of the
number of ports being read.  That is, a single port read performance
would be degraded when additional ports were added.  The scheme
presented here allows for optimization of read performance regardless
of the number of ports being read concurrently.

      Fig. 1 illustrates the schematic representation of a single
port write L3 latch base cell and associated read port transfer gate
selector, which are used to build the array portion of the L3 CACHE.
In this illustration, two read ports are implemented.  The
illustration uses CMOS n-p transfer gate pairs for the write and read
ports.  This can be replaced by n type only transistors if the
electrical characteristics are sufficient or other implementations
can be utilized.

      Fig. 2 illustrates the connection of L3 latches described in
Fig.  1 to form a single column (bit 0, words 0-N) of an L3 array.
As seen from this figure, the read ports are each selected by an
address decoder.  Hence, port A can read the contents of word 0;
while port B can read the contents of any word, including word 0.
When the addresses to the read decoders are different, then the read
ports will select different words and hence different latches will be
driving the respective ports.  When the addresses to the read
decoders are equal, then both ports A and B will read the same memory
location, and therefore that selected memory location will be
required to drive twice the capacitive load and result in degraded
performance.  Since the overall performance is limited to the
worst-case scenario, the multi-port read operation from a common
location limits the performance.

      Fig. 3 illustrates a configuration of four Exclusive OR (XOR)
circuits and a four-input NOR used to detect when the read addresses
for ports A and B are equal.  The example being used here is for a
16- word CACHE, and hence the limit of four inputs for the address
decode.  Any word length can be implemented.  Into each XOR circuit
are the corresponding address bits being supplied to the respective A
and B port address decoders.  That is, one XOR is supplied th...