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Multi Bit Step Up/Down Counter With One/Zero Detect Capability

IP.com Disclosure Number: IPCOM000099437D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Ikeda, T: AUTHOR [+4]

Abstract

From an application standpoint step up or down counters are commonly used logic networks. Such counters may be used as an instruction counter, microinstruction counter for control store, shift counters, or timer in a computer clock, or watch. They are also useful for updating addresses and word counts in DMA channels.

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Multi Bit Step Up/Down Counter With One/Zero Detect Capability

       From an application standpoint step up or down counters
are commonly used logic networks.  Such counters may be used as an
instruction counter, microinstruction counter for control store,
shift counters, or timer in a computer clock, or watch. They are also
useful for updating addresses and word counts in DMA channels.

      The basic operation of this network is shown in Fig. 1. A
binary number is put on one of the ports of the counter. The control
signal for decrementing is set to one and the decrement operation is
started.  Decrementing continues until all zeros is reached at which
point a flag is sent out to some other location on the chip.  A new
binary number is inserted into the counter from a different port and
the control signal for incrementing is set to one and the
incrementing operation is started.  Incrementing proceeds until a
binary number consisting of all ones is reached at which point a flag
is raised and sent out to some destination.

      This network is extremely dense and uses a minimum number of
devices which translates into efficient silicon usage.  It has been
physically designed utilizing a custom bit slice approach.  The
advantages of a custom bit slice approach versus a standard cell
implementation is high density and fast circuitry.  These benefits
are significant.

      The novelty of this invention lies in the circuitry associated
with the incremen...