Browse Prior Art Database

Built-in Self-Test Technique for Speed Sorting of VLSI Chips

IP.com Disclosure Number: IPCOM000099445D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 123K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR [+2]

Abstract

The use of a built-in self-test (BIST) technique in performance sorting of VLSI chips provides a very cost-effective alternative to the current technique of doing performance sorting by using smart tests coded by the chip designers, who must have a very detailed knowledge of the chip logic and the tester language.

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Built-in Self-Test Technique for Speed Sorting of VLSI Chips

       The use of a built-in self-test (BIST) technique in
performance sorting of VLSI chips provides a very cost-effective
alternative to the current technique of doing performance sorting by
using smart tests coded by the chip designers, who must have a very
detailed knowledge of the chip logic and the tester language.

      The current technique of doing speed sorting of VLSI chips
consists of the following steps:

      1. The chip designer, who has a very detailed knowledge of the
chip logic, analyzes his logic and identifies the most critical paths
on his chip.

      2. The chip designer then writes a functional testcase, that is
supposed to exercise the most critical paths (longest path delays) on
the chip.

      3. The functional testcase is then mapped into tester language
(assuming that the methodology exists to do that) and the tester
executes the testcase against the DUT (Device Under Test) at varying
clock rates (or oscillator frequency) until the chip fails the test-
case.  At this point, the chip is believed to have reached its maxi
mum functional speed. Continued The previous approach has the
following disadvantages: .Only the chip designer can analyze his
logic and identify the most critical paths.  This may not be possible
in all cases. Certainly it is not trivial, and requires a great
engineering judgment to be exercised. .Writing a functional testcase
to exercise the most critical paths is not easy, is time-consuming
and assumes that the logic designer has a close working relationship
with the test engineer. .Mapping the speed sorting functional
testcase into a tester language testcase may not always be possible,
in most cases, because of inade  quacies or insufficiencies in the
design and test methodology. .Because the performance sorting
functional testcase aims at exercis  ing the most critical path or
just a few paths on the chip, there is a potential of an error in
determining how fast the chip is.  The error occurs when a delay
path, not targeted in the speed sort testcase, is rendered
unexpectedly slower than the most critical paths tested.  This
usually results from variations in the manufac  turing process
parameters and is more likely to happen with the lar  ger physical
sizes of VLSI chips.  To minimize this risk, more than just the most
critical path and as many delay paths as possible should be tested.
.A logic critical path may not necessarily include a path through an
embedded array which can be easily mapped into a tester language
testcase. THE BIST TECHNIQUE

      Using BIST as a technique to achieve speed sorting works as
follows: Continued .Pseudorandom test vectors are generated by
hard...