Browse Prior Art Database

System Bus Tag Ram

IP.com Disclosure Number: IPCOM000099446D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 104K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+2]

Abstract

This article describes a technique for use in a computer system whereby the amount of cache snoop-overhead is reduced by duplicating part of the tag RAM (random-access memory) for the CPU's cache on the system bus. When bus masters write to system memory, caches in the system must be alerted (called snooping) of the write operation to maintain coherency.

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This is the abbreviated version, containing approximately 52% of the total text.

System Bus Tag Ram

       This article describes a technique for use in a computer
system whereby the amount of cache snoop-overhead is reduced by
duplicating part of the tag RAM (random-access memory) for the CPU's
cache on the system bus.  When bus masters write to system memory,
caches in the system must be alerted (called snooping) of the write
operation to maintain coherency.

      Fig. 1 is a representation of a typical system, which comprises
CPU, cache, memory, memory/bus controller, and system bus.  The
system bus may contain additional memory (system bus memory) and bus
masters.  When the CPU executes a memory read cycle, the local bus
cache control- ler checks the local bus tag RAM for an address match.
 If an address match (cache hit) occurs, then the requested data is
returned by the local bus cache memory rather than by the slower
planner memory or system bus memory.  If an address match does not
occur then the data from that memory location is retrieved and stored
in the local bus cache and the address is stored in the local tag
RAM.

      In a dual bus system, a bus master and the CPU may operate
concurrently.  Since the bus master may modify system bus memory that
has been previously cached in the local bus cache, there is a
potential for the CPU to use stale data.  The following scenario
illustrates the problem. The CPU reads a system bus memory location
and the data is cached in the local bus cache.  A bus master writes
new information to the same location in system bus memory.  The CPU
reads that location in system bus memory again, but stale data is
provided by the local bus cache.  This problem may be alleviated by
requiring the bus master to execute an invalidate cycle (post the
address on CPU cache on the local bus) for each bus master write to
system bus memory.  The disadvantage to this scheme is that often the
cycle is wasted, since the probability of a bus master accessing
system bus memory that has been cached in the local bus cache is low.

      Fig. 2 is a block diagram of the system shown in Fig. 1 with
the addition of a system bus tag RAM.  The system bus tag RAM is a
subset of the local bus cache tag RAM and contains only the tags
ass...