Browse Prior Art Database

High-speed LSSD Shift Register Loading

IP.com Disclosure Number: IPCOM000099447D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Motika, F: AUTHOR [+3]

Abstract

This article describes a procedure for reducing the test time associated with loading/unloading SRL string(s) during LSSD functional test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-speed LSSD Shift Register Loading

       This article describes a procedure for reducing the test
time associated with loading/unloading SRL string(s) during LSSD
functional test.

      Testing of LSSD (Level-Sensitive Scan Design) logic product (*)
requires multiple loading/unloading of Shift Register Latch (SRL)
string(s).  The length of the string can vary from a few latches for
a low density logic chip to thousands for a multi-chip module (MCM)
with single or multiple SRL strings.  Presently, SRLs are
loaded/unloaded by applying data to the shift register input (SRI)
receiver and pulsing the A clock followed by the B clock, as shown in
Fig. 1.  This is then repeated for the number of latches in the SR
string.  With chips containing multiple SRLs, the loading/unloading
is performed simultaneously for all SRLs. The shifting operation is
repeated until the longest SR loading is satisfied.  One can see from
Fig. 1 that the maximum rate at which the tester can shift the SRL is
limited by the timing accuracy between multiple tester channels (edge
placement accuracy, repeatability and channel skew), which is very
difficult and expensive to minimize in tester hardware.

      To improve tester throughput the authors propose employing only
a single tester channel to generate the timing reference for the
shift operation and supply data to the SRI.  The A and B clocks are
then generated internally (onboard) by the chip using this reference.
 The SRI channel can be used in a time-multiplexed mode to accomplish
this, as shown in Fig. 2, where the leading edge of the SRI data is
the timing reference for the internally generated A and B clock
pulses.  The other timing requirement on the SRI is that the data be
valid (0 or 1) when it is strobed into the SRL by the internally
generated A clock.

      The A and B clock pulses can be generated...