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Parallel Local Operator Engine And Fast P300

IP.com Disclosure Number: IPCOM000099448D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 6 page(s) / 264K

Publishing Venue

IBM

Related People

Dom, BE: AUTHOR [+3]

Abstract

This article describes an architecture that may be configured as a SIMD fine-grained parallel processor or it may be configured as an SIMD/MIMD hybrid, with multiple rows of processors, where all the processors in a given row are executing exactly the same instructions, but each row is programmed differently. A variation of the architecture that uses a "Z-net" for directly passing data over large distances within the processor array will also be described. The algorithms for which this architecture is designed are those that may be formulated as operators that produce a result for each pixel in the image based on the values of the pixel itself and some set of its neighbors, though not necessarily its nearest neighbors. A simple example of such an operator would be an NxN convolution.

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Parallel Local Operator Engine And Fast P300

       This article describes an architecture that may be
configured as a SIMD fine-grained parallel processor or it may be
configured as an SIMD/MIMD hybrid, with multiple rows of processors,
where all the processors in a given row are executing exactly the
same instructions, but each row is programmed differently.  A
variation of the architecture that uses a "Z-net" for directly
passing data over large distances within the processor array will
also be described. The algorithms for which this architecture is
designed are those that may be formulated as operators that produce a
result for each pixel in the image based on the values of the pixel
itself and some set of its neighbors, though not necessarily its
nearest neighbors.  A simple example of such an operator would be an
NxN convolution.  This architecture is called the Parallel Local
Operator Engine (PLOE).  Also described is a scheme for executing the
P300[&P300.,&P3PAT.] and similar algorithms for inspection of
repetitive patterns such as memory, array and CCD photosensor chips.

      Basic Architectural Components:  The architecture to be
described is fed by some image acquisition device, whose output is
either a serial stream of digital greyscale pixel values (8-bit is
most common) or multiple serial data streams from a device such as a
multi-tapped linear CCD array. (Unless otherwise stated, all data
paths will be assumed to be as wide as the number of bits of grey
scale being used.  Eight bits is most common for systems of this
type.)

      1.  The data stream from the acquisition device feeds a serial-
in/parallel-out shift register one scan line (N pixels) long, one per
section of the input device.

      2.  Adjacent to the shift register(s) is an array of processors
configured so that each shift register position feeds one column of
processors when the register is read out in parallel mode.  These
processors have the following attributes:  (1) They may have
relatively simple instruction sets:  add, subtract, compare and
branch;  (2) They need to handle the number of greyscale bits
required;  (3) They should be designed to be elements of a
4-connected mesh. That is they will have at least four bidirectional
I/O ports (N,S,E, and W) each with its own input and output
registers; (4) An option is to have a fifth bidirectional data port
(call it "Z") if the "programmable switch" scheme (to be described
later) is used.

      3.  South of the processor array is a parallel-in/serial-out
shift register for reading results out of the array.

      High-Level Control Structure:  A high-level control structure
initiates, coordinates and terminates the operation of the PLOE
processor array and provides an interface with a host computer.  This
structure is for the most part a standard SIMD control.  Those places
where it must be unique will be obvious from the following
discussion.

      General ...