Browse Prior Art Database

Technique for a "dynamic" Burn-in Test

IP.com Disclosure Number: IPCOM000099450D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 90K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR

Abstract

This invention describes a technique for performing a 'dynamic' burn-in test. Previous burn-in test techniques achieved static burn-in tests that did not exercise the combinational logic within the chip circuit. This technique employs BIST (Built-In Self-Test) sequences to exercise the sequential AND combinational logic within the circuit, thus, leading to a more complete burn-in test.

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Technique for a "dynamic" Burn-in Test

       This invention describes a technique for performing a
'dynamic' burn-in test.  Previous burn-in test techniques achieved
static burn-in tests that did not exercise the combinational logic
within the chip circuit.  This technique employs BIST (Built-In
Self-Test) sequences to exercise the sequential AND combinational
logic within the circuit, thus, leading to a more complete burn-in
test.

      The burn-in test consists of exercising the DUT (Device Under
Test, board, chip, etc.) under extreme environmental conditions
(temperature, humidity, etc.) for long hours. The part is then
removed from the environmental test chamber and retested for
functionality with a predefined manufacturing test.  Because of the
limitation in the number of wires and cables that can connect the
tester to the DUT inside the environmental chamber and other
logistical problems, burn-in tests, in most cases, consisted of
continuously applying scan data to the DUT scan strings using only
scan clocks.  These burn-in tests are referred to as static burn-in
tests because:

      1. The test is not necessarily conducted at the clock rate of
the DUT.

      2. The test does not exercise the combinational logic because
the clocks used during the test are either scan clocks or clocks used
in scan mode.

      By using a BIST (Built-In Self-Test) sequence defined early in
the design cycle and by having the necessary BIST support and control
logic implemented and integrated on the chips (see Fig. 1), it is
possible to achieve a dynamic burn-in test.

      The tester issues a series of commands to a BIST controller
residing on every chip.  These controllers are shown in Fig. 1 and
are referred to as c1 thro...