Browse Prior Art Database

Delay Start And Control Off

IP.com Disclosure Number: IPCOM000099457D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Clemmons, E: AUTHOR [+2]

Abstract

This article describes a method and circuit enablement which controls application and removal of voltage to communications circuits, thereby preventing transition spikes which could impact data integrity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Delay Start And Control Off

       This article describes a method and circuit enablement
which controls application and removal of voltage to communications
circuits, thereby preventing transition spikes which could impact
data integrity.

      The proper application of voltage during start up is critical
to the operation of particular circuits.  The proper removal of
voltage is critical to the integrity of transmitted data at turn-off.
The circuit disclosed herein delays the application of voltage until
the voltage is at the rated level and applies the voltage fast at
turn on.  At turn off this circuit will monitor the sensed voltage
and remove the voltage fast when the voltage decreases to a
predetermined value.

      The circuit of this disclosure is shown in the drawing. A
field- effect transistor (FET) Q1 acts as an on/off switch for the
control of the Vin (+5 V).  When the gate of Q1 is at a high
level, Q1 is on and the Vin (+5 V) is output (Vout).  When the gate
of Q1 is low, Q1 is off and the Vin voltage is switched off.  Vout
is low level.

      A ZM1 module which includes comparators ZM1-A and ZM1-B acts as
the control for the gate of the transistor Q1.  The outputs of ZM1
are connected to the gate of transistor Q1 so that if either or both
outputs are low then transistor Q1 gate is low and it is off.  If
both outputs of ZM1 are off (voltage out of ZM1 is high), then
transistor Q1 gate is high, Q1 is on, and the Vout (+5 V) is the
output.

      The circuit operates as set forth below. Turn On:

      The +12 V and Vin (+5 V) are both at 0 V to start.
Both voltages begin to increase.  The gate of transistor Q1 is low.
Q1 is off.  As the voltages increase, the voltage at the zener diode
CR1 will increase with the applied voltage (+12 V).  The zener diode
CR1 will clamp the zener voltage at the specified zener voltage.  The
zener voltage is connected to the negative input of comparator ZM1-A.
 The positive input of comparator ZM1-A is connected through resistor
R3 to capacitor C.  Capacitor C is charged through resistor R1 from
the +12 V.  The slow charge of capacitor C provides for the delay
voltage on the negative input of comparator ZM1-A.  At a specified
time determined by the resistors R1, R2 and capacitor C1 values, the
voltage on the positive input of ZM1-A will exceed the zener diode
CR1 voltage on the negative input if the ZM1-A comparator output
changes to an up level.

      Comparator ZM1-B negative input is connected to the resistor
divider R5 and R6.  The divider network is connected to the zener
diode CR1.  As stated above, zener diode CR1, connected to the +12 V
through...