Browse Prior Art Database

Dynamic Power Management by Clock Speed Variation

IP.com Disclosure Number: IPCOM000099483D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Bantz, DF: AUTHOR [+2]

Abstract

Disclosed is a technique for exploiting the speed-dependent power-consumption characteristic of CMOS logic under software control. The technique offers finer-grained power control for interactive personal computers than those currently in practice.

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Dynamic Power Management by Clock Speed Variation

       Disclosed is a technique for exploiting the
speed-dependent power-consumption  characteristic  of  CMOS  logic
under software control. The technique offers  finer-grained  power
control   for  interactive  personal  computers  than  those
currently in practice.

      Current practice for power  control  requires  explicit
shut-down  of  subsystems  or of the processor of a personal
computer, often based on a timer together  with  a  lack  of
interactive   activity.    Hardware  detection  of  activity
(monitoring of the interrupt facility) turns  the  processor back on.

      What  is  disclosed  here  is  a  technique  for  power
conservation that can make use of very  short  intervals  of idleness
 between  bursts  of  processing,  by varying clock speed.  The
invention consists of, on the one hand, a  clock chip  capable  of
producing a range of clock rates, together with a register to hold
the clock rate specification, and on the other hand, instructions
which may be  I/O  instructions to   set  that  register.
Operating  systems  capable  of multitasking invariably maintain a
list of  tasks,  some  of which  are  ready  to  run  and  others  of
which may not be dispatched because they are waiting for some event
to occur. It is relatively easy for the task dispatcher  component
of the  operating  system to detect the conditio...