Browse Prior Art Database

New Electroplating Gold Process to Improve Calibration of E-beam Tool

IP.com Disclosure Number: IPCOM000099503D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Ruyer, JP: AUTHOR [+2]

Abstract

Highly integrated semiconductor devices are made by high quality mask process using E-beam tool to write images. To solve overlay problem, a calibration of E-beam tool is necessary. To this end, a gold grid consisting of a 300 X 300 array of 5 micron crosses spaced by linewidths of 37.5 microns is used to achieve calibration.

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New Electroplating Gold Process to Improve Calibration of E-beam Tool

       Highly integrated semiconductor devices are made by high
quality mask process using E-beam tool to write images. To solve
overlay problem, a calibration of E-beam tool is necessary. To this
end, a gold grid consisting of a 300 X 300 array of 5 micron crosses
spaced by linewidths of 37.5 microns is used to achieve calibration.

      The standard fabrication process is based upon a typical
bipolar device lift-off process. This process induces high defect
density as resist residues, gold remaining and so on, which alters
the precision of beam positioning during the writing for future
advanced products. To overcome these inconveniences a new process is
disclosed below. This process allows depositing gold crossed lines
between vertical wall in 10 class clean concept conditions.

      NEW PROCESS DESCRIPTION CLEAN wafer
           (silicium or quartz) EVAPORATE chrome plating base
                  (300 to 1000 Ao) EVAPORATE a flash of gold APPLY
first resist layer (POLYIMIDE 20000 Ao) APPLY resist layer
                         (1500 to 5000 Ao) EXPOSE AND DEVELOP resist
                          (MEBES III 10 KeV) TRANSFER image through
first layer             (plasma tool RIE mode, oxygen/helium)
ELECTRODEPOSIT gold (20000 Ao) STRIP resist (plasma) ETCH chrome
                    ...