Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Buffer Circuit With Delayed Rising Or Falling Transition for Pulsewidth Skew Control

IP.com Disclosure Number: IPCOM000099511D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Verhaeghe, M: AUTHOR

Abstract

A circuit to compensate the delay skews in a circuit chain is described in this article.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Buffer Circuit With Delayed Rising Or Falling Transition for Pulsewidth Skew Control

       A circuit to compensate the delay skews in a circuit chain
is described in this article.

      The input inverter of the buffer has a resistive path in one
leg of the switching device.

      Adding an "on" P transistor in series with the switching P
transistor will slow down the rising edge of the input inverter and,
therefore, the falling edge of the buffer. This will produce a pulse
expansion.

      Adding an "on" N transistor in series with the switching N
transistor will slow down the falling edge of the input inverter and,
therefore, the rising edge of the buffer. This will produce a pulse
shrinkage.

      The added delay is a function of the power supply, temperature,
W/L ratio threshold voltage, etc., and therefore tracks with delays
of other circuit laid out on the same chip.

      Adding "on" transistors in one leg of the switching device
slows down one transition, but does not alter the other transition
(Fig. 1).

      There is no impact on the input capacitor since the N or P
transistors gates are not connected to the buffer input.

      Several resistive paths of different characteristics can be
connected in parallel to increase delay capability.

      Fig. 2 shows a way to provide several shrinkage values by means
of conduction of one or several transistors of T1, T2, T3, etc.