Browse Prior Art Database

Adaptive High-Speed CRC Generator/Checker

IP.com Disclosure Number: IPCOM000099515D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 162K

Publishing Venue

IBM

Related People

Goldstein, BC: AUTHOR [+3]

Abstract

This article describes an adaptive circuit for a high-speed CRC Generator/Checker which supports a data throughput speed of 560 Mbit/second. The circuit allows CRC (cyclic redundancy code) checking/generation on selectable packet lengths. The choice of which packet length is to be used is a function of the BER (bit error rate). This circuit allows us to use the existing VLSI technology to achieve our goal of a high-speed CRC circuit. Background

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Adaptive High-Speed CRC Generator/Checker

       This article describes an adaptive circuit for a
high-speed CRC Generator/Checker which supports a data throughput
speed of 560 Mbit/second.  The circuit allows CRC (cyclic redundancy
code) checking/generation on selectable packet lengths.  The choice
of which packet length is to be used is a function of the BER (bit
error rate).  This circuit allows us to use the existing VLSI
technology to achieve our goal of a high-speed CRC circuit.
Background

      In high-speed Data Communications the BER is low, but errors
occur in bursts due to fluctuations in the output power of the laser
driver.  A good link protocol design should not restrict the packet
size of the data since flexibility in this parameter allows the link
to adapt to large burst errors.  Longer packets should only be
transmitted in low BER environments and shorter packets should be
sent during times of high BER.  Our circuit allows for this type of
adaptation by keeping statistics on both packet size and packet error
count.

      In High-Speed Full-Duplex Fiber-Optic Transmission a pair of
fibers is used, one for transmission and one for reception.  The Data
Link Control functions are divided into two major blocks, one for
transmission and one for reception.  These two blocks communicate
with each other via control messages which are sent during the
acknowledgment of received packets or during requests for
re-transmission of erroneous packets.  The CRC remainder is generated
with each packet transmission by the CRC generator.  The CRC is
checked at the receiver by the CRC checker to determine if an error
has occurred.  One of the bottle necks in high-speed communications
is to generate the CRC remainder at the speed of the High-Speed Link.
 One way of solving this problem is by using a high-speed technology
to support the Link speed.  With this new high-speed environment and
low BER, the packet size to optimize the use of the total bandwidth
and minimize the transmit delay should be large. However, the smaller
the packet, the greater the error detection capability of the CRC
polynomial. Circuit Description

      In our invention we utilize existing technology to achieve
high- speed CRC generation and checking.  We have allowed the packet
size to vary in accordance with the BER. The figure shows the
transmit (TX) and receive (RX) circuits for CRC generation and
checking.  The TX circuit consists of the following major blocks:

      TX Memory - configured as 128k by 32 bits - receives the data
from the Network Layer which is to be transmitted.
    Byte Count - stores the packet size to be transmitted.
    Sequencer - controls the TX memory handshaking and the 32 to 8
MUX-to-CRC Generator interface.

      CRC Generator - generates the remainder at the end of the data
frame, i.e., 16, 32, 48 or 56 bytes.

      Parallel-to-Serial Converter - converts 8 parallel bits of data
to a seri...