Browse Prior Art Database

Power Grid Image for Embedded Arrays

IP.com Disclosure Number: IPCOM000099522D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Buettner, SW: AUTHOR [+2]

Abstract

This article describes a power line grid by which embedded arrays are rotated and mirror-placed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Power Grid Image for Embedded Arrays

       This article describes a power line grid by which embedded
arrays are rotated and mirror-placed.

      The existing power line grid image (Fig. 1) allows
mirror-placing macros with an X-X mirror axis but no rotation.  There
are two second metal power lines VH, GND located in the center of the
basic module.  Such a structure does not permit rotating and
mirror-placing with a Y-Y mirror axis.  The basic module defines the
power grid image.

      It is proposed that in lieu of one VH line in the second metal,
two such lines be used, and that the right line GND be moved into the
Y-Y symmetry axis of the basic module (Fig. 2).

      The two second metal VH lines can be readily shorted by the
first metal power lines.  First-to-second metal vias are added.  The
new power image allows macros (embedded arrays) being placed in a
variety of ways.  180o rotation and mirror-placing with X-X and Y-Y
mirror axes may be used for chip layout.  This greatly enhances the
chip wiring, since macros may be placed in an optimum fashion.  The
I/O location of the macros can be chosen such that the chip-to-chip
wiring (e.g., the bus wiring) on multi-chip modules is short (low
capacitance).  Minimum cycle times (short wires) are more readily
obtainable.