Browse Prior Art Database

Processor Architecture for Measurement And Monitoring Functions

IP.com Disclosure Number: IPCOM000099533D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 6 page(s) / 280K

Publishing Venue

IBM

Related People

Genduso, TB: AUTHOR

Abstract

A technique is described whereby a computer processor incorporates an architecture that assures the ability to measure and monitor performance functions of a system. The architecture is designed to provide the ability to study the behavior of different operational environments during a processor's normal functions. It is an improvement over interrupt driven measurement and monitoring structures (1,2), which can have a negative impact on performance and can limit the type of data that can be gathered. The design is unique in that performance data can be gathered without incurring the overhead of a processor interrupt.

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Processor Architecture for Measurement And Monitoring Functions

       A technique is described whereby a computer processor
incorporates an architecture that assures the ability to measure and
monitor performance functions of a system.  The architecture is
designed to provide the ability to study the behavior of different
operational environments during a processor's normal functions.  It
is an improvement over interrupt driven measurement and monitoring
structures (1,2), which can have a negative impact on performance and
can limit the type of data that can be gathered.  The design is
unique in that performance data can be gathered without incurring the
overhead of a processor interrupt.

      With the advent of higher density very large-scale integrated
(VLSI) circuitry, many of the signals used to conduct performance
mea- surements are no longer externally accessible, making electrical
mea surements virtually impossible to conduct.  The concept described
herein incorporates, within a processor's architecture, a hardware
instruction set that can be applied to any processor family and then
used for the purposes of measuring and monitoring the performance.
It is designed so that it assures the ability to measure a
processor's operational performance through many generations of
implementations.

      The measurement and monitoring architecture extends to the
software environment in which the hardware operates. Four fundamental
assumptions are made regarding the software environment:
1. A software supervisory performance monitor program would exist as
part of the system's supervisory code. This monitor program would run
in the privileged state and would control and manage the mechanisms
provided by the hardware architecture in a consistent manner.  An
application would use a software interface to access the architecture
by way of the software supervisory performance monitor.
2. The system would assign an area in real storage for the collection
of performance data.  The exact size and location is determined and
controlled by the system. Before a trace is made, this area of
storage must be initialized.
3. All program modules would incorporate the monitoring feature and
would include a unique identification code. The identification code
can be transferred from a general- purpose register to the processor
bus as part of a performance monitoring (PMON) instruction.  A bit
would be used to indicate the start/end of a program module so as to
allow for tracing of the modules performance in a running system with
no change to the code.  To minimize the impact on the performance of
a running system, "tagging" is implemented only on certain selected
modules.  By defining a field with thirty-two bits, the capability of
performing a trace by module type can be developed.
4. PMON is a privileged instruction.

      The units which perform the measurement and monitoring
functions, as shown in Fig.  1, consist of data collectors (...