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Browse Prior Art Database

Shadow Latch for Boundary Scanning

IP.com Disclosure Number: IPCOM000099534D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Hardell, WR, Jr: AUTHOR [+3]

Abstract

One method of testing the internal logic of chips is to put the chip latches in a scan mode and shift data from one latch to another. Fig. 1 shows how latches might be connected for boundary scanning, where "boundary" refers to the latches that drive chip outputs.

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This is the abbreviated version, containing approximately 100% of the total text.

Shadow Latch for Boundary Scanning

       One method of testing the internal logic of chips is to
put the chip latches in a scan mode and shift data from one latch to
another. Fig. 1 shows how latches might be connected for boundary
scanning, where "boundary" refers to the latches that drive chip
outputs.

      In some system configurations the outputs cannot toggle during
boundary scanning.  Described is a method to allow boundary scanning
of important information without adding logic between the boundary
latches and drivers while forcing the outputs to a known state
(preventing the outputs from toggling).

      This boundary scan implementation uses shadow latches in the
boundary scan string.  Also, by using shadow latches, the outputs can
be forced to a known state during boundary scan without putting logic
between the latch and the driver. The output latches can be put in
their own scan string (possibly for tester usage).

      Fig. 2 shows how the shadow latch can be connected.  The data
input for the shadow latch is from the internal logic that needs to
be checked by boundary scan.  The functional (output) latch will
clock in a known state during boundary scanning.