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Paralleling Links in a Unified Switching Architecture for Circuit/Packet Switching

IP.com Disclosure Number: IPCOM000099547D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 190K

Publishing Venue

IBM

Related People

Engbersen, A: AUTHOR [+4]

Abstract

Switching Structures which interconnect transmission links by transferring minipackets between these links usually treat each input link and each output link separately. In some applications, the information rate to be transmitted exceeds the capacity of a single link. In order to compensate for this limitation, multiple links must be operated in parallel. The following description explains how this can be achieved.

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This is the abbreviated version, containing approximately 40% of the total text.

Paralleling Links in a Unified Switching Architecture for Circuit/Packet Switching

       Switching Structures which interconnect transmission
links by transferring minipackets between these links usually treat
each input link and each output link separately.  In some
applications, the information rate to be transmitted exceeds the
capacity of a single link.  In order to compensate for this
limitation, multiple links  must be operated in parallel.  The
following description explains how this can be achieved.

      Switching System Structure:  The structure of a unified
switching system can be seen in Fig. 1.  This figure shows the
structure broken down into its four major functional areas. The
center portion is a memory labeled (1).  The element labeled (2)
performs the management of the memory such that it logically behaves
as n first-in, first-out (FIFO) queues.  The elements labeled (3)
perform the serial receive and packet address decode of incoming
packets.  This decode results in a request for entry into a specific
FIFO where this packet should be queued.  The elements labeled (4)
perform the fetching of packets from a specific FIFO for
serialization onto the output link.

      FIFO Control:  Fig. 2 diagrams the major functions within the
FIFO control section.  This diagram only depicts a single FIFO
control element and this control element is replicated as many times
as there are output links to enable each output to have a separate
FIFO.  The common memory is partitioned into a set of sections
defined by each of the TOP and BOTTOM registers.  These registers
enable a specific FIFO to be located anywhere within the common
memory and to be of any size.  Initially, the NEXT-IN pointer and the
NEXT-OUT pointer are set equal to the value in the TOP register.
When an input packet has been received and the destination  FIFO has
been decoded, the packet will be stored in the FIFO at the
appropriate location.  The NEXT-IN pointer will be incremented by the
length of the packet, ready for the next requestor.  When the NEXT-IN
pointer becomes equal to the value in the BOTTOM register, the
NEXT-IN pointer will be set to the value of the TOP register, thus
operating the FIFO as a circular buffer whose length is equal to the
difference between the values in the TOP and BOTTOM registers.
Likewise, the NEXT-OUT pointer of each FIFO control is operated in
the same manner, with the OUTPUT segments requesting the value in the
NEXT-OUT pointer, and the NEXT-OUT pointer being incremented by the
length of the packet.  It is also compared with the value in the
BOTTOM register and when equal is set to the value of the TOP
register.  To prevent loss, additional circuitry is added to indicate
when the FIFO is full (i.e., the NEXT-IN pointer is one packet space
less than the NEXT-OUT pointer). The FIFO indicates empty when the
value in the NEXT-OUT pointer has advanced to equal the value in the
NEXT-IN pointer.

      Inp...