Browse Prior Art Database

State Machine Glitch Catcher

IP.com Disclosure Number: IPCOM000099550D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Hill, KL: AUTHOR [+2]

Abstract

Disclosed is a method of removing erroneous signal transitions on signals that last for more than one state in a state machine design. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

State Machine Glitch Catcher

       Disclosed is a method of removing erroneous signal
transitions on signals that last for more than one state in a state
machine design.

                            (Image Omitted)

      In a state machine design, situations can occur that cause
erroneous transitions on signals that last for more than one state
machine state, or that must last from one state to the next.  This
situation is particularly bothersome if the time slices are directly
related to the state machine clock.  This can cause glitches on the
state machine decodes even if only one variable changes from one
state to the next.

      The problem can be corrected by adding an extra latch, which
then becomes part of the time slice decode.  The latch is clocked
with a signal that is related to the clock of the state machine.  The
latch is set prior to the state transition of interest, and is held
until after the state transition of interest.  Since it is part of
the time slice decode, it removes the uncertainty at the state
transition boundary, and the decode is now stable.