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Buffer With Fast Cycle Time for Data Transfers Between Main Memory and I/O Devices

IP.com Disclosure Number: IPCOM000099570D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

Capowski, RS: AUTHOR [+6]

Abstract

In some data processing systems, a large number of I/O devices are connected to the main memory of a central processor by a funnel-shaped network of buses. Many users at a lower level share buses and other resources at the higher levels, and the network is characterized by nodes where several narrower buses at a lower level are connected to a single wider bus at a next higher level. Channels, which make up one of the levels, each have a bus and other components. Nodes at some levels have a buffer memory. Some nodes are a connection point between the channels and a processor called IOP that performs certain operating system functions for the channels.

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Buffer With Fast Cycle Time for Data Transfers Between Main Memory and I/O Devices

       In some data processing systems, a large number of I/O
devices are connected to the main memory of a central processor by a
funnel-shaped network of buses.  Many users at a lower level share
buses and other resources at the higher levels, and the network is
characterized by nodes where several narrower buses at a lower level
are connected to a single wider bus at a next higher level.
Channels, which make up one of the levels, each have a bus and other
components.  Nodes at some levels have a buffer memory. Some nodes
are a connection point between the channels and a processor called
IOP that performs certain operating system functions for the
channels.

      A new buffer is provided for a node where, e.g., four buses
from a lower level are connected to a single bus of the next higher
level.  The four buses on the channel side of the buffer each have a
data width that is designated one data unit.  The single bus on the
processor side has a width of two data units.

      Internally, the buffer and its input and output registers have
a width of four data units.  Separate registers are provided for
assembling data units from the processor side and from the channel
side before the data units are transferred to the buffer memory input
register for a buffer operation.  Two buffer cycles are required for
assembling four incoming data units on the processor side, and four
b...