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Low-Threshold Short-Channel Mosfet With Punch-Through Protection

IP.com Disclosure Number: IPCOM000099591D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15

Publishing Venue

IBM

Related People

Vinal, AW: AUTHOR

Abstract

Short channel MOS source-drain punch-through is pre- vented for drain voltage below 10 volts while simultaneously allowing for independent control of threshold sensitivity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 23% of the total text.

Low-Threshold Short-Channel Mosfet With Punch-Through Protection

       Short channel MOS source-drain punch-through is pre-
vented for drain voltage below 10 volts while simultaneously allowing
for independent control of threshold sensitivity.

      Punch-through is the primary voltage breakdown mechanism in
conventional short-channel MOSFET devices.  The usual methods of
control- ling punch-through result in increases in the diffusion
capacitance and threshold voltage of the device.  Breakdown and
threshold voltage are summarized in Table 1 as a function of channel
length.  A punch-through barrier technique is described.  The barrier
substantially increases the maximum operating drain voltage that can
be utilized below a well- controlled punch-through value.  In
addition, the gate threshold sensitivity may be independently
controlled.  The result is a short-channel enhancement-mode P or N
channel MOS device that possesses both low threshold and high
breakdown voltage.

      A simple self-aligned fabrication process is also disclosed
that represents an economic advantage for new barrier MOS technology.
 Hot electron effects may be minimized by the barrier MOS design
along with its reduction in gate and diffusion capacitance.

      This article describes a new MOSFET design that effectively
prevents punch-through from occurring prior to the inevitable
ionization breakdown.  The design allows independent control over the
threshold voltage and its sensitivity to source voltage without
influencing punch-through or the avalanche (ionization) breakdown
criterion.

      Figs. 1A through 1C illustrate cross-sectional views of typical
MOSFETS and show the events leading up to the source-drain punch-
through condition.  A discussion of these prior devices is briefly
included as an aid to understanding the novel structures in Figs. 2
through 5.

      Fig. 1A illustrates a typical N-channel MOSFET configuration.
The source and drain are initially shown at ground potential with a
gate voltage Vg in excess of a threshold voltage Vt, resulting in the
creation of an inversion layer or channel.  A depletion region 7 is
also shown surrounding the source and drain diffusions and extending
below the inversion layer of the channel.  The depletion layer 7
penetrates into the P type substrate at a distance or depth measured
outward from the source or the drain of Xp0 or Xpd, respectively.
The penetration depth intrinsically resulting from an abrupt source
or drain to substrate junction is given by equation 1: (1)

                            (Image Omitted)

 where V  =
drain or source voltage. es = dielectric constant for silicon
(1x10-12 Farads/cm) Na = acceptor concentration cm-3 Nd = donor
concentration cm-3

      Fig. 1B illustrates how growth in the depletion layer
surrounding the drain diffusion occurs with increasing drain and gate
voltages.  This occurs as the drain voltage is incr...