Browse Prior Art Database

DC-DC Converter Synchronization for Reduction of EMI in Fault-tolerant Systems

IP.com Disclosure Number: IPCOM000099592D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Brandl, TA: AUTHOR

Abstract

This article describes a circuit arrangement for synchronizing DC-to-DC power converters in a fault-tolerant system by means of a master oscillator whose frequency can be increased by means of a passive component on the back panel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

DC-DC Converter Synchronization for Reduction of EMI in Fault-tolerant Systems

       This article describes a circuit arrangement for
synchronizing DC-to-DC power converters in a fault-tolerant system by
means of a master oscillator whose frequency can be increased by
means of a passive component on the back panel.

      Broadband electromagnetic interference (EMI) radiation is
produced by the sum and difference frequencies that result from
unsynchronized switching power conversion of parallel regulators.
The problem is especially troublesome for high frequency (20 kHz -
500 kHz) as well as for parallel systems with a long input power
conductor.  The problem can be compounded by a design restriction
against a system master clock, for whatever reason.

      The figure shows the circuit arrangement disclosed herein.
Power supply regulator integrated circuits operate with a
RC-controlled oscillator.  The resistor and capacitor components are
attached externally for designer selection of operating frequency,
which is inversely proportional to the product RC.

      Usually, for a bank of parallel regulators, the oscillators of
each are designed for the same frequency.  If synchronization is
desired, a master clock signal is usually provided from an external
source.  For synchronization to be successful, the master must be 10%
faster than the slave it is to override.  The approach presented
herein provides for an increase in frequency of the master module or
a decrease of the slave modules' frequency, and synchronization
signal routing.  This is accomplished with identically built modules
and a backpanel module with only passive components on it.

      This approach designates the master as any module that is
plugged into the master slot as shown in the drawing. Consequently,
the master slot must be the first slot to be filled and the last to
be emptied for the synchronization t...