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L3 Lssd Latch Arrangement Schemes Which Permit 100% Cache Array Lssd Testing

IP.com Disclosure Number: IPCOM000099598D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 8 page(s) / 295K

Publishing Venue

IBM

Related People

Correale, A: AUTHOR [+3]

Abstract

L3 latch arrangements have been used extensively to implement small CACHE memories. These implementations resulted in the use of functional test patterns with little or no diagnostic capabilities for testability as the use of LSSD patterns could not provide 100% coverage of ensuing logic (e.g., bit decoders). The pattern coverage problem stems from the implementation of the CACHE array and decoder scheme utilized. The techniques described below will, each in their own right, solve the problems that have plagued testability. The implementation of either of these schemes will also allow the integration of L3 CACHE arrays to be used on chips where self-test is the primary test vehicle without the test coverage loss.

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L3 Lssd Latch Arrangement Schemes Which Permit 100% Cache Array Lssd Testing

       L3 latch arrangements have been used extensively to
implement small CACHE memories.  These implementations resulted in
the use of functional test patterns with little or no diagnostic
capabilities for testability as the use of LSSD patterns could not
provide 100% coverage of ensuing logic (e.g., bit decoders).  The
pattern coverage problem stems from the implementation of the CACHE
array and decoder scheme utilized. The techniques described below
will, each in their own right, solve the problems that have plagued
testability. The implementation of either of these schemes will also
allow the integration of L3 CACHE arrays to be used on chips where
self-test is the primary test vehicle without the test coverage loss.

      Fig. 1 illustrates the schematic representation of a single
port L3 latch base cell used in previous cache designs.  Both
functional and LSSD scan data are applied to the data port of the
latch.  The write select is the logical OR of the write address
location and the P clock (test clock).

      Fig. 2 illustrates the connection of L3 latches described in
Fig.  1 to form a single column (bit 0, words 0-N) of an L3 array.
As seen from this figure, the data ports of all L3 latches within a
column are common.  During functional operation, the write select
line activates the row of L3's to be written.  Only one L3 latch
within a given column will be selected.  However, during LSSD test
mode, all latches will be simultaneously loaded with data via
activation of the P clock.  All latches within a given column will be
loaded with the same value since the scan/data input to these latches
is driven from a common L1 latch.  This L3 latch arrangement is shown
in Fig. 3.

      Since the contents of all latches within a given column contain
the same data, fault isolation in the downstream logic (i.e., read
selector and buffers) is not possible. The voltage at node A is the
same whether or not there are read select stuck at faults.  For
example, if read select 0 is stuck at "1" while any other read select
has been activated, the value at node A is determined by the L3 latch
contents.  As each latch contains the same value, there is no way to
determine the stuck fault condition.  Hence, the key to improving the
LSSD test coverage of the downstream logic is to be able to (a) load
different values in the L3 latches within a given column or (b)
design a read decoder arrangement wherein no read port is selected
during test. Both of these options are discussed at length in the
following paragraphs.

      The first option discussed is the use of L3 latch with dual
port write capability.  This is illustrated by the schematic
representation shown in Fig. 4.  Data is loaded into the latch with
the write select line, which is now only the decoded row address.
The second port allows the scan-in data to be loaded into the latch
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