Browse Prior Art Database

Charge Shared Sense Line

IP.com Disclosure Number: IPCOM000099639D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Sunaga, T: AUTHOR

Abstract

Disclosed is a circuit configuration to realize fast stabilization of a sense amplifier input level by a charge-sharing mechanism between a bit line and a data line in semiconductor memories.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Charge Shared Sense Line

       Disclosed is a circuit configuration to realize fast
stabilization of a sense amplifier input level by a charge-sharing
mechanism between a bit line and a data line in semiconductor
memories.

      In semiconductor read-only memories (ROMs), one sense amplifier
per data output is used.  According to address data, a bit switch
circuit selects a bit line and connects it to a common data line.
The sense amplifier input is connected to the common data line.
Because many cells, usually 256-1024, share the metal bit line, bit
line capacitance due to diffusion and wiring is high.  The common
data line also has many diffusion nodes.  Total capacitance of the
bit and data lines becomes as high as a few picofarads.  Since a
small cell transistor must discharge the large capacitance, it
requires a long time for the sense amplifier to detect a voltage drop
on the data line.

      Fig. 1 shows the present circuit configuration.  It assumes
multi- state ROM, and therefore, cell currents are personalized to
non-zero multi-level by threshold voltages or geometrical variations
of the cell transistors.  T3 is the memory cell NMOSFET and T1 is its
PMOSFET load.  T2 is a bit line restore transistor.  It precharges a
bit line, BL, to VDD.  T4 is a bit switch to connect the bit line
and a data line, DL. T6 pulls the data line down during standby.  Ics
works as a current sink during the data line voltage rising.  Fig. 2
shows a timing chart.  RE is a restore signal.  WL and COL are a word
line and a column line of the ROM, respectively. In standby, RE, WL,
and CSW are low.  COL and SS are high. T4 is off.  The bit line
is at VDD, and the data line is held at ground.  The current sink,
Ics, is off.

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