Browse Prior Art Database

Read-Only Memory With Double Pitch Pull-Up Pets

IP.com Disclosure Number: IPCOM000099649D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Sunaga, T: AUTHOR

Abstract

Disclosed is a circuit configuration to implement a large PMOSFET pull-up load in a narrow pitch memory array.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Read-Only Memory With Double Pitch Pull-Up Pets

       Disclosed is a circuit configuration to implement a large
PMOSFET pull-up load in a narrow pitch memory array.

      A mirror current generation circuit is widely used in many CMOS
circuit applications.  In a read-only memory (ROM), it is used to
detect a cell current.  A PMOSFET pull-up load is connected to the
drain of a NMOS cell transistor.  A sense amplifier compares the
mirror current of the cell with that of a reference cell.  Because
bit lines of the memory array are usually laid out at a minimum pitch
of first level metal lines which is determined by the technology
used, it is very difficult to use the large PMOS pull-up transistor
for each bit line.  A single PMOS pull-up transistor is therefore
connected to a data line which is a common sense amplifier input for
many bit lines.  According to decoded address inputs, bit switch
selects a bit line and connects it to the data line.  Fig. 1 shows
this circuit configuration.  The left half of Fig. 1 is the mirror
current circuit of the memory cell transistor, TC, and the right half
is that of the reference cell, TR.  TFC and TFR are transfer gates of
the bit switch.  A DC current due to the cell flows from TPC to TFC
and TC.  Another DC reference current flows from TPR to TFR and TR.
Because these two DC currents are different, voltage drops across the
transfer gates, TFC and TFR, are also different.  The transfer gates
therefore cause erroneous mirror currents in TMC and TMR.

      Fig. 2 shows the...