Browse Prior Art Database

Read-Only Memory With Active Pull-Down Circuit

IP.com Disclosure Number: IPCOM000099651D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Sunaga, T: AUTHOR

Abstract

A circuit configuration to speed up bit line discharge in semiconductor memory chips is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Read-Only Memory With Active Pull-Down Circuit

       A circuit configuration to speed up bit line discharge in
semiconductor memory chips is disclosed.

      In one-transistor read-only memories (ROMs), bit line
capacitance is one of the major factors to degrade access time.  If a
cell current is small, it takes a long time for the bit line voltage
to decrease low enough that a sense amplifier can detect the voltage
drop correctly.  The situation becomes more severe for a 4-state ROM
in which cells are personalized by 4 different threshold voltages
(Vth).  The highest Vth cell does not conduct until the word line
voltage exceeds the threshold voltage.  Its cell current is small
because of a low gate-to-source voltage. The 4-state ROM usually has
longer access time than conventional ROMs.

      Fig. 1 shows the present circuit configuration.  TC is an
NMOSFET cell of a ROM and TP is its PMOSFET pull up load. WL and
COL are a word line and a column line of the cell, respectively.  A
cell current is mirrored to another PMOSFET, TM, and a sense
amplifier detects the current.  TR1 and TR2 are restore transistors
for a bit line, BL, and a data line, DL, respectively.  They pull BL
and DL up to VDD, when RE is low.  CB and CD are bit and
data line capacitances, respectively.  They are usually a few
picofarads.  TDC is a data line pull down NMOSFET with its gate
connected through an AND to a word line delay detection circuit
(WLDD).  The AND receives RE...