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Multiprecision Barrel Shifter

IP.com Disclosure Number: IPCOM000099656D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Buttimer, MD: AUTHOR [+3]

Abstract

Disclosed is a technique of using a multiplexer formed by combinations of logic to implement a barrel-shifter/rotator of data strings, such as computer operands, which can be of fixed or defined variable lengths. The novel feature of the design is that multiprecision results may be obtained for iterative shifter operations. The circuit arrangement is also simpler while providing a level of function basically similar to conventional designs. The logic is driven from signals obtained from stored definitions of data lengths and the required function selected by a decode of the instruction's operation code. The design has been implemented.

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Multiprecision Barrel Shifter

       Disclosed is a technique of using a multiplexer formed by
combinations of logic to implement a barrel-shifter/rotator of data
strings, such as computer operands, which can be of fixed or defined
variable lengths.  The novel feature of the design is that
multiprecision results may be obtained for iterative shifter
operations.  The circuit arrangement is also simpler while providing
a level of function basically similar to conventional designs.  The
logic is driven from signals obtained from stored definitions of data
lengths and the required function selected by a decode of the
instruction's operation code.  The design has been implemented.

      Background Typical shift instructions listed in the table below
perform arithmetic and logical shifts.  All but the EXTEND
instruction operate on word-length data and produce a word-length
result.  The EXTEND instruction operates on double-word data and
produces a word-length result.  If both parts of the double-word for
the EXTEND instruction are from the same source, the EXTEND operation
is equivalent to a rotate operation.  For each operation, the shift
count is a 5-bit integer, specifying a shift amount in the range of 0
to 31 bits.

      The New Circuit

      The figure shows a block diagram of the shifter/rotator
designed for a 32 bit data flow.  Note that = signifies bit
replication to the indicated number.  The shift/rotate signals
supplied by the processor are:-
           LENGTH              (5 bits)
           + RIGHT             (- left)
           + ROTATE            (- shift)
           + ARITHMETIC MODE   (- logic)
           + EXTEND            (Multiprecision shift
     operations only)

      The operation of the circuit for single precision shifts will
be described initially.

      Single Precision Shifts The selective negator at block A
creates a standardized 'right' length, RLEN, thus converting a shift
left length 2 into a shift right length 30, for example (left lengths
will be passed through block A unmodified).  The details of block A
are described in an article en titled "Selective Negator" published
in the IBM Technical Disclosure Bulletin, Vol. 30, No. 6, November
1987, at pages 434-436.  RLEN is then used by the multiplexers in the
right rotator at block H to effect the shift/rotation.  However,
before right rotation, the data supplied by the processor may need to
be modified according to the type of operation (shift or rotate,
logical shift or arithmetic, single or multiprecision).  This
modification is produced primarily through the use of a series of
1-bit 2:1 selectors (block G) where, for any g...