Browse Prior Art Database

Dynamic Clock Frequency Changing for a Memory Controller

IP.com Disclosure Number: IPCOM000099660D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 6 page(s) / 308K

Publishing Venue

IBM

Related People

Bates, MD: AUTHOR [+3]

Abstract

The novelty of the disclosed concept resides in the close coupling of a memory controller with the portion of the clock generator which produces clock pulses (clocks) for the memory controller. The memory controller, besides controlling memory, is capable of causing the clock generator to change the frequency of the clocks it receives. In a Dynamic Clock Frequency Change mode, the clocks of the memory controller are alternately matched to the frequency of the main processor and matched to the frequency or timing granularity of the control's signals required by DRAM memory devices. This capability avoids the need for an asynchronous interface between the main processor and the memory controller. The disclosed concept has been implemented.

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Dynamic Clock Frequency Changing for a Memory Controller

       The novelty of the disclosed concept resides in the close
coupling of a memory controller with the portion of the clock
generator which produces clock pulses (clocks) for the memory
controller.  The memory controller, besides controlling memory, is
capable of causing the clock generator to change the frequency of the
clocks it receives. In a Dynamic Clock Frequency Change mode, the
clocks of the memory controller are alternately matched to the
frequency of the main processor and matched to the frequency or
timing granularity of the control's signals required by DRAM memory
devices.  This capability avoids the need for an asynchronous
interface between the main processor and the memory controller.  The
disclosed concept has been implemented.  Knowledge is assumed in this
disclosure of the operation of Dynamic Random-Access Memory (DRAM)
devices, design of Very Large-Scale Integration (VLSI) integrated
circuits and Level-Sensitive Scan Design (LSSD).

      Introduction The speed of a Dynamic RAM (DRAM) memory device is
normally quoted in terms of its minimum data access from the falling
edge of RAS.  At present, typical available DRAMs have data access
time from RAS of 80ns, 100ns, 120ns and 150ns.  The other timing
parameters of a DRAM memory device are usually scaled in direct ratio
to the minimum data access time from RAS.  For instance, the minimum
data access time for a 150ns DRAM is usually 75ns; for a 120ns DRAM,
it is 60ns; and so on.  The basic timing granularity of a DRAM is
normally half the quoted data access time from RAS; thus, a 120ns
DRAM may be operated with control signals at a granularity of 60ns.
Discussion here relates to DRAM memory devices but also applies to
Video RAM (VRAM).

      The ability of a memory controller to handle different speeds
of DRAM memory gives the system designer a choice of
price/performance trade-offs in the design of a memory system.  DRAMs
with shorter data access times are capable of greater speed of
operation (higher performance) but are more expensive.  This
disclosure considers a VLSI pro DYNAMIC cessor chip which runs at a
processor cycle time of 100ns and must be capable of accessing DRAM
memory devices with data access times of either 100ns or 150ns.  The
VLSI processor chip is also available in a "speed-sorted" version
with a processor cycle time of 80ns, which must be capable of
accessing DRAM memory devices with data access times of either 80ns
or 120ns.  The speed ratio of 1.5 (2:3) is chosen to illustrate this
disclosure, because it is considered an "awkward" ratio.  The
concepts described are by no means limited to this ratio.  The VLSI
processor chip contains the main processor itself, the memory
controller, a clock generator and other circuitry which may also
access the attached DRAM through the memory controller.  The memory
controller must develop all the signals used in the control of t...