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Diagnostic Register-read in LSSD

IP.com Disclosure Number: IPCOM000099666D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Buttimer, MD: AUTHOR [+4]

Abstract

This disclosure describes a method of reading the contents of a VLSI chip using the LSSD scan chains. In an LSSD design, all shift register latches (SRLs) are directly linked together by one or more scan chains. The operations performed by a design are defined by the static logic between registers and the conditions under which those registers are loaded. The scan chains are not utilized in the logical operations that are performed between register outputs and register inputs. (If one or more SRLs behave as a single entity, that entity is referred to as a register.) The state of a design at any given time, is uniquely defined by the contents of all the registers in that design. The state of a design may change every clock cycle, the new state being a function of the previous state and the primary inputs to the design.

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This is the abbreviated version, containing approximately 52% of the total text.

Diagnostic Register-read in LSSD

       This disclosure describes a method of reading the
contents of a VLSI chip using the LSSD scan chains.  In an LSSD
design, all shift register latches (SRLs) are directly linked
together by one or more scan chains.  The operations performed by a
design are defined by the static logic between registers and the
conditions under which those registers are loaded.  The scan chains
are not utilized in the logical operations that are performed between
register outputs and register inputs.  (If one or more SRLs behave as
a single entity, that entity is referred to as a register.) The state
of a design at any given time, is uniquely defined by the contents of
all the registers in that design.  The state of a design may change
every clock cycle, the new state being a function of the previous
state and the primary inputs to the design.  It is extremely
expensive, in terms of silicon area and general circuit complexity,
to make every register in a design externally readable by
conventional logical paths.  This disclosure shows how the scan
chains, inherent in an LSSD design, can be used efficiently to scan
out the current state of the design, by the simple control of LSSD
clocks.

      In a conventional LSSD chip, all the registers are joined by a
single scan chain, although in VLSI chips multiple scan chains may be
used to reduce testing time.  At power-up time the chip is
initialized by forcing a binary '0' or '1' down the scan chains.
This is achieved by forcing 'A' clock high, 'B' clock high, and 'C'
clock low. By carefully controlling the A, B and C clocks, it is
possible to strobe the chip in a manner that enables a host system to
capture the data held in the LSSD registers.  To achieve this, the
scan chains are broken into two types, scan chain type 1 and scan
chain type 2.  Scan chai...