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Quaternary Logic Channel for Binary Logic Interconnection

IP.com Disclosure Number: IPCOM000099667D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 6 page(s) / 206K

Publishing Venue

IBM

Related People

Barcelo, P: AUTHOR [+3]

Abstract

This article describes a circuit arrangement wherein binary signals are transferred from one binary logic circuit to another binary logic circuit by converting the binary signals to quaternary signals and transferring them through a quaternary transmission channel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Quaternary Logic Channel for Binary Logic Interconnection

       This article describes a circuit arrangement wherein
binary signals are transferred from one binary logic circuit to
another binary logic circuit by converting the binary signals to
quaternary signals and transferring them through a quaternary
transmission channel.

      Increases in circuit density on very large-scale integrated
(VLSI) circuits have reached a point where the most important
limitation is no longer the number of gates on a chip, but the number
of pins on a chip.  Applications that naturally employ large numbers
of input/output (I/O) lines are not able to take full advantage of
the high circuit densities available in modern VLSI modules.  For
example, modules are being produced for parallel processing
applications that contain several processors within the module,
however, due to the multiple buses being used, the limiting factor is
the number of I/O pads on the module.  In this example, if a method
were available to provide more buses without increasing the number of
pins on the module, more processors can be added inside the module
and the high circuit densities of VLSI can be taken advantage of to a
greater extent.

      A similar problem is encountered when a bus (channel) must be
cabled from one card to another.  The cabling is limited by the
number of pins on the connector and/or by the number of connectors
able to fit off the edge of a card. Also, the size of a bus
may be restricted by the space on a back panel or mother board.  All
of these problems could be solved if more information could be
represented on a single line.

      A method by which binary signals are transferred from one
binary logic circuit to another binary logic circuit by converting
the binary signals to trinary or (ternary) signals and transferring
them through a trinary transmission channel is shown in [*].  Just as
binary logic is a digital system based on two logic states (0,1),
trinary logic is a digital system based on three logic states
(0,1,2).  By converting to trinary, every three binary lines are
converted to two trinary lines, reducing the number of I/O
interconnections to two thirds of a conventional parallel binary
transmission channel.

      Presented here is a method to reduce the number of I/O
interconnections to one half of a conventional parallel binary
transmission channel.  Binary signals are transferred from one binary
logic circuit to another binary logic circuit by converting the
binary signals to quaternary signals and transferring them through a
quaternary transmission channel.  Quaternary logic is a digital
system based on 4 states (0,1,2,3).  The use of quaternary logic not
only reduces the number of I/O interconnections required by either
binary or trinary systems, but it also produces a more direct and
therefore more efficient conversion.  By using this method, every two
binary lines are converted to one quaternary line. ...