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Wordline Redundancy Control Circuit for Cmos Dynamic Memories

IP.com Disclosure Number: IPCOM000099674D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+4]

Abstract

Disclosed is a control circuit for wordline redundancy in CMOS dynamic memories. The unique features are a self-timed trigger using one wordline address in addition to array selection signal AS and an asymmetric half-latch for precharging the fuse NOR nodes. The circuit is designed to prevent current surges during the precharge time and to provide the same performance as regular operation with no RAS access time penalty.

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This is the abbreviated version, containing approximately 52% of the total text.

Wordline Redundancy Control Circuit for Cmos Dynamic Memories

       Disclosed is a control circuit for wordline redundancy in
CMOS dynamic memories.  The unique features are a self-timed trigger
using one wordline address in addition to array selection signal AS
and an asymmetric half-latch for precharging the fuse NOR nodes.  The
circuit is designed to prevent current surges during the precharge
time and to provide the same performance as regular operation with no
RAS access time penalty.

      The schematic of the wordline redundancy control circuit is
shown in Fig. 1.  It includes the redundancy control circuit for two
redundant wordlines RDWDA and RDWDB. One of these is activated when
the redundancy operation starts.  Basically, the circuit uses dynamic
NOR decoders for wordline decoding.  The normal or redundancy mode is
determined by the status of fuse NOR node A or B after wordline
addresses are set.  In standby, AnT and AnC, which are the true and
complement pair of each wordline address, are low, and nodes A and B
are precharged to VDD through T1 and T2. In the normal mode, PRASDI
rises and turns precharging devices T1 and T2 off before AnT and AnC
are set.  Here, the PRASDI signal is generated from the RAS signal.
As AnT and AnC set, nodes A and B fall to GND through Tn devices
turned on and a regular wordline is activated.  If wordline
redundancy fuses are programmed and the corresponding address comes,
node A or B stays in the high state because all of the Tn...