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Bitline Redundancy Control Circuit for CMOS Dynamic Memories

IP.com Disclosure Number: IPCOM000099676D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+4]

Abstract

Disclosed is a control circuit for bitline redundancy in CMOS dynamic memories. The unique features are a dynamic NOR decoding circuit using PMOS active load, and an asymmetric half-latch for precharging the fuse NOR node. In addition, the circuit saves power by gating the precharge device off after each CAS access using PCAS rising edge triggered signal.

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Bitline Redundancy Control Circuit for CMOS Dynamic Memories

       Disclosed is a control circuit for bitline redundancy in
CMOS dynamic memories.  The unique features are a dynamic NOR
decoding circuit using PMOS active load, and an asymmetric half-latch
for precharging the fuse NOR node.  In addition, the circuit saves
power by gating the precharge device off after each CAS access using
PCAS rising edge triggered signal.

      The schematic of the circuit is shown in Fig. 1.  Fig. 2 shows
the simulated waveforms of the circuit.  The normal or redundancy
mode is determined by the status of fuse NOR node A after the bitline
address is set.  In the standby state, the node A is held at GND by
T1. When PXI is activated to a high level, T1 turns off, and at the
same time, the node A is precharged to VDD through T2 by NORing of
inverted PXI and AS.  Here, PXI signal is derived from the wordline
clock, and AS is the signal for selecting one of several independent
arrays.  In the normal case with no fuse programmed, the node A falls
to GND as Tn devices turn on when the various AnT or AnC, which are
true and complement signals of each of each bitline address, become a
high state.  If bitline redundancy fuses are programmed and the
corresponding address comes, node A stays high because all of the Tn
still connected to node A are off and the redundancy mode starts.
The high state of node A is latched by the asymmetric half-latch.
Consequently, the RB signal is act...