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Browse Prior Art Database

Fast BI-CMOS XOR-NOT Circuit

IP.com Disclosure Number: IPCOM000099679D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

The fast BI-CMOS XOR-NOT circuit hereafter described uses BICMOS MULTI- BASE type of circuit as taught in published European Patent Application No. 0318 624. It is possible to build a very fast XOR-NOT because the circuit uses the NAND type of MULTI-BASE circuits which is the fastest in that logic family. The circuit resulting therefrom has higher speed than other known XOR or XOR-NOT built with other techniques using standard BI-CMOS technology.

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Fast BI-CMOS XOR-NOT Circuit

       The fast BI-CMOS XOR-NOT circuit hereafter described uses
BICMOS MULTI- BASE type of circuit as taught in published European
Patent Application No. 0318 624. It is possible to build a very fast
XOR-NOT because the circuit uses the NAND type of MULTI-BASE circuits
which is the fastest in that logic family. The circuit resulting
therefrom has higher speed than other known XOR or XOR-NOT built with
other techniques using standard BI-CMOS technology.

      As shown in Fig. 1, the XOR-NOT circuit is comprised of 2
circuits connected in series. The first one is a traditional NAND2
MULTI-BASE.  The second one is a 2 by 2 OAI (OR-AND-INVERTER) with
one dropped input.

      The speed of the second stage is very high, because the
worst-case path is given by the NAND2 portion of circuit of the OAI,
and more particularly by NFETs N1, N4 and PFET P1. The other part of
the second circuit is an OR structure which is slower but receives
the A and B input signals before the NAND between A and B input
signals is performed.

      There is given now an example of implementation. In a
traditional Full Adder circuit, the sum is built with a 3 input XOR
based on two  2 input XORs connected in series. The same function can
now be built with two XOR-NOT circuits connected in series providing
the higher speed for such a circuit in a BI-CMOS logic circuit
family.