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Bi-CMOS Inverter in One Equivalent CMOS Gate-Array Cell

IP.com Disclosure Number: IPCOM000099685D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

In a conventional CMOS gate-array using 3P/3N MOS cells and gate isolation technique, a BI-CMOS cell has been implemented, featuring one bipolar transistor, one resistor, and CMOS devices (Fig. 1).

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Bi-CMOS Inverter in One Equivalent CMOS Gate-Array Cell

       In a conventional CMOS gate-array using 3P/3N MOS cells
and gate isolation technique, a BI-CMOS cell has been implemented,
featuring one bipolar transistor, one resistor, and CMOS devices
(Fig. 1).

      This implementation shows a one equivalent cell impact on the
CMOS row of the gate-array. This is obtained by having a polysilicon
resistor, a bipolar transistor sharing N-WELL with the PMOS devices,
and ROX isolation technique on the NMOS row side. Due to technology
constraints, design has to be optimized so that it can fit in such a
small space.

      The value of the resistor, nominal current of bipolar pull-up,
as well as CMOS device widths obtained, allow to efficiently build a
high power inverter (Fig. 2), with only one cell of the gate-array.