Browse Prior Art Database

Self Power-Off Bi-CMOS Driver

IP.com Disclosure Number: IPCOM000099689D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Leforestier, S: AUTHOR [+2]

Abstract

This article describes a BI-CMOS driver. It is intended to drive very heavy capacitive load. The application of this driver in this case is to provide a signal to drive highly capacitive (5 to 10 pF) word lines in high density SRAMs. This driver is set on a very short negative transition on its input, which has only to be equal to the driver propagation delay (i.e., the clock can be depowered as soon as the word line is up). The driver keeps its output value even if the clock signal is raised. An internal signal will restore the driver, and will reset the driver at its 0 level.

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Self Power-Off Bi-CMOS Driver

       This article describes a BI-CMOS driver. It is intended
to drive very heavy capacitive load. The application of this driver
in this case is to provide a signal to drive highly capacitive (5 to
10 pF) word lines in high density SRAMs. This driver is set on a very
short negative transition on its input, which has only to be equal to
the driver propagation delay (i.e., the clock can be depowered as
soon as the word line is up). The driver keeps its output value even
if the clock signal is raised. An internal signal will restore the
driver, and will reset the driver at its 0 level.

      This article is directed to a new type of BI-CMOS driver with
no DC power, with dynamic-electrostatic set and reset; in this
particular case, the reset is provided internally, and the driver
behaves as a single-shot circuit.

      Circuit Description (see the figure) The power push-pull is
composed with the NPN transistors T1 and T2. P1 drives the base of
the pull up T1 with a signal coming from the decoder. The transistors
P2, N2, N7 are used to insure a correct low level on the word lines
in order to avoid any cell leakage that could SELF increase the SRAM
dissipation dramatically. When the word line is raised through T1, a
raising transition propagates through the inverter P2-N5 and P3-N6,
that signal will self-reset the driver through the N devices N2 and
N4.  The intent of the reference generator (T5, R2, R3) is to speed
up the base of t...