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Multi-Purpose Trench for Complementary Metal Oxide Silicon, Six-Device Static Random-Acess Memory Cell

IP.com Disclosure Number: IPCOM000099691D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Plass, DW: AUTHOR

Abstract

A high-density static random-access memory (SRAM) cell is achieved by using a conductive polysilicon filled trench for isolation, latch-up control and as a ground wire to the cell.

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Multi-Purpose Trench for Complementary Metal Oxide Silicon, Six-Device Static Random-Acess Memory Cell

       A high-density static random-access memory (SRAM) cell is
achieved by using a conductive polysilicon filled trench for
isolation, latch-up control and as a ground wire to the cell.

      As is shown in the figure, the P+ polysilicon filled trench 2,
having oxidized sidewalls 4, is in good electrical connection with
the P+ substrate 14, while being electrically isolated from (and
separating) the N-well 6 and P-epitaxial silicon 8 regions.  This
arrangement serves as isolation between PMOS and NMOS areas,
defeating the lateral NPN parasitic bipolar transistor and thereby
preventing latchup.  A silicide bridge 10 is formed by a salicide
process to connect the Nsource/drain 12 to the grounded P+ substrate
14 via the conductive trench polysilicon 2.  This method of obtaining
the ground connection saves space and results in a very low
resistance path to ground.  The P+ source/drain 16 (which also has a
silicide layer on top) remains isolated from the polysilicon trench
due to the presence of the recessed oxide (ROX) region 18.