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Contact Process Providing Layout Advantages in a Static Random-Access Memory Cell

IP.com Disclosure Number: IPCOM000099692D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

DeBrosse, JK: AUTHOR [+3]

Abstract

A process is described which allows making selective contacts between gate conductor and a local interconnect level of wiring requiring only low precision area masking (borderless). Thus, a local interconnect may make contact with gate wiring at one point and cross over and be insulated from gate wiring at another point. This process proves advantageous in achieving a high density complementary metal oxide silicon (CMOS) static random-access memory (SRAM) cell.

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Contact Process Providing Layout Advantages in a Static Random-Access Memory Cell

       A process is described which allows making selective
contacts between gate conductor and a local interconnect level of
wiring requiring only low precision area masking (borderless).  Thus,
a local interconnect may make contact with gate wiring at one point
and cross over and be insulated from gate wiring at another point.
This process proves advantageous in achieving a high density
complementary metal oxide silicon (CMOS) static random-access memory
(SRAM) cell.

      Referring to Fig. 1, standard CMOS processing is used to create
N-well 10 in substrate 8, isolation insulator 12, gate oxide 14, and
gate conductor 16.  Then, an insulating cap 18 is deposited.  An
opening 20 is etched in cap 18 where it is desired that contact be
made to a gate conductor during subsequent local interconnect
formation.  Gate conductors are then defined in photoresist.  Exposed
cap 18 is etched away first and then gate conductor 16 is removed
leaving cap 18 only on gate conductor areas not selected for
contacts.

      Referring to Fig. 2, standard CMOS processing is used to make
sidewall spacers 22 and source and drain diffusions 24, 26, 30, and
32.  Local interconnect wiring 28 is deposited and defined.  Source
and drain regions 30 and 32 and selected gate conductor 34 underlying
wiring 28 are contacted while other gate conductors are not
contacted. Gate conductor 36 crosses under and...