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Browse Prior Art Database

BI-CMOS Multi-Base Integrated Complementary Logic Circuits

IP.com Disclosure Number: IPCOM000099693D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

The disclosed circuits are improvements to circuitry described in published European Patent Application No. 0318624. The circuit shown in the figure is based on the use of complementary NPN and PNP transistors in emitter follower mode driven by CMOS logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

BI-CMOS Multi-Base Integrated Complementary Logic Circuits

       The disclosed circuits are improvements to circuitry
described in published European Patent Application No. 0318624. The
circuit shown in the figure is based on the use of complementary NPN
and PNP transistors in emitter follower mode driven by CMOS logic.

      The two-way NAND has two top NPN (Multi-Emitter) and one bottom
PNP transistors to have a high driving capability. When both inputs
are at one, the PNP turns on with a base current through the NFETs N1
and N2.  When one of the inputs is low, either NPN1 or NPN2 is "ON",
giving the UP level on the output.

      OUT DOWN going transition: for the DOWN going transition, node
BP is not slowed down by crossover current and capacitance of devices
P1 and P2; since nodes BN1 and BN2 are pulled down quickly by the
NFETs NUP1 and NUP2 at the speed of an inverter (devices P1/NUP1 and
P2/NUP2), which is faster than a NAND circuit. The size of the NFETs
NUP1 and NUP2 can be reduced, compared to P1 and P2 as they are just
used to discharge the base capacitance node.

      OUT UP going transition: for the UP going transition, output
node OUT is not slowed down by BP because BP is quickly pulled up by
one of the PFETs PDN1 or PDN2.  As for NUP1 and NUP2, the size of
the PFETs PDN1 and PDN2 can be reduced.

      Globally, an OR pull-up logic is performed by emitter dotting
of transistors NPN1 and NPN2 while a NAND pull-down logic is
performe...