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BI-CMOS LSSD Latch With an Extendable Logic Input

IP.com Disclosure Number: IPCOM000099695D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+4]

Abstract

A new BI-CMOS latch circuit which can be used in the LSSD (Level-Sensitive Scan Design) concept is described in the following. To design this latch a tri-state type of circuit has been used with the capability to extend the input function to NAND, NOR, etc., and other base logic circuits.

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This is the abbreviated version, containing approximately 56% of the total text.

BI-CMOS LSSD Latch With an Extendable Logic Input

       A new BI-CMOS latch circuit which can be used in the LSSD
(Level-Sensitive Scan Design) concept is described in the following.
To design this latch a tri-state type of circuit has been used with
the capability to extend the input function to NAND, NOR, etc., and
other base logic circuits.

      The circuit is shown in the figure.  The storage cell is made
with two CMOS inverters tied in a latch structure. NFETs NL1, N9 and
NF PFETs PL1, PU are used to build the latch cell.

      To simplify the scheme of the figure, the scan path of the LSSD
concept with clock signal A and scan-in data "I" is not represented.

      The clock signal C is distributed to the control circuit in and
out of phase. The DATA "D1" and "D2" are generated "in phase" only.

      When the clock input is high, the data is stored in the latch.
Transistor NPN TD1 is maintained off by NFET N5 in the on state.
Transistor NPN TUP is on only if the output of the latch -L1 is at
the up level.

      When the clock is at the down level (ON), one of the NPN
control transistor TD1 or TUP is "on" depending on the DATA (D1, D2)
value. The state of the latch is maintained or changed to its
opposite state.  During the transitions the bipolar transistors are
active, allowing high speed operation with high capacitance loading.
NFETs N1 and N2 which are in series, performs the AND of the input
Data D1 and D2 during the write. To write...