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Test Structure for Measuring Non-Inverting CMOS Circuit Delays

IP.com Disclosure Number: IPCOM000099697D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Gouze, E: AUTHOR [+2]

Abstract

The so-called McLeod's loops were devised to indepen- dently extract rising and falling transition times (Ton and Toff) logic circuits from oscillation frequency measurements. This technique turned out to be unusable for CMOS circuits, however, due to inaccuracies inherent to the structure. A modified approach is proposed for non-inverting CMOS circuits only, which does not exhibit these problems and allows picosecond accuracy measurement of both delays.

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Test Structure for Measuring Non-Inverting CMOS Circuit Delays

       The so-called McLeod's loops were devised to indepen-
dently extract rising and falling transition times (Ton and Toff)
logic circuits from oscillation frequency measurements. This
technique turned out to be unusable for CMOS circuits, however, due
to inaccuracies inherent to the structure. A modified approach is
proposed for non-inverting CMOS circuits only, which does not exhibit
these problems and allows picosecond accuracy measurement of both
delays.

      Fig. 1 illustrates the basic McLeod's loops schematic for non-
inverting circuits. Two paths, connected to a common feedback delay
line, can be selected for oscillation either one at a time, like in
standard ring oscillators, or together in a path shifting mode.

      The oscillation periods as a function of the command line
states can be expressed by the following equations:
-    Cmd0 = 0, Cmd1 = 1: 'reference' path as a ring
 oscillator
 period1 = Ton(A+E) + Toff(A+E) + K(feedback)
-    Cmd0 = 1, Cmd1 = 0: 'test' path as a ring oscillator
     with the CUT (Circuit Under Test) connected in series
      period2 = Ton(B+CUT+E) + Toff(B+CUT+E) + K(feedback)
-    Cmd0 = 0, Cmd1 = 0: race condition, which causes the
     rising edges of the reference path and the falling
     edges of the test path to propagate into the feedback
     chain.
      period3 = Ton(A+E) + Toff(B+CUT+E) + K(feedback)
      By subtracting two of the measured periods, one gets:
      Ton(CUT) = period2 - period3
      Toff(CUT)= period3 - period1

      These equations are valid provided the following conditions are
met:
      a) blocks A and B have the same delays;
      b) block E has the same delays whatever the active
      path; and
      c) the feedback line delays are constant.

      This is the case when the McLeod's loops are implemented with
bipolar logic circuits. It is not the case with CMOS circuits since
their performances are much more sensitive to switching conditions,
such as activated input pin, input signal transition time and load
capacitance.

      Referring to the above conditions, one can notice that i...