Browse Prior Art Database

High Density Dram Cell (Q-Elope Cell)

IP.com Disclosure Number: IPCOM000099705D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 150K

Publishing Venue

IBM

Related People

Chin, D: AUTHOR [+2]

Abstract

In future high density DRAMs, the cell must be as small as possible. A DRAM cell whose area can be close to the theoretical minimum of 4 squares is shown in the schematic layout of the cell in Fig. 1. There are, however, difficulties in achieving the minimum-area cell. Metal- to-diffusion contact sites are one limiting area. The contact site presently requires borders against isolation as large as one minimum feature size because of lateral encroachment of bird's beak and overlay tolerance. The other technical problem is related to two deep-trench- etching processes which will be discussed later.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Density Dram Cell (Q-Elope Cell)

       In future high density DRAMs, the cell must be as small
as possible. A DRAM cell whose area can be close to the theoretical
minimum of 4 squares is shown in the schematic layout of the cell in
Fig. 1.  There are, however, difficulties in achieving the
minimum-area cell.  Metal- to-diffusion contact sites are one
limiting area.  The contact site presently requires borders against
isolation as large as one minimum feature size because of lateral
encroachment of bird's beak and overlay tolerance.  The other
technical problem is related to two deep-trench- etching processes
which will be discussed later.

      In the fabrication process, two sidewalls of the storage trench
filled with polysilicon form Hi-C type capacitors for the two
neighboring cells.  Fig. 2 shows the cross section of the cell across
the wordline direction. The storage trenches are isolated by deep
trenches filled with oxide in the bitline direction, as shown in Fig.
3.  The storage trench was made by a self-aligned RIE with the
isolation trench and polysilicon gates.  Since a trench, however,
becomes narrower towards the bottom, this tapering of the isolation
trench will result in a short between two adjacent storage nodes
which share the same trench. Therefore, a positive tapering trench is
necessary.  Another potential problem is that since the cell uses
only one trench sidewall for storage capacitance, a deeper trench is
necessary to obtain sufficient capacitance.  It thus requires a
larger trench opening than the minimum-feature size to obtain
sufficient depth, and thus a 4-square cell is even more difficult to
achieve.  This article describes a novel technique that realizes
contacts without requiring additional area and, at the same time,
solves the difficulty in removing the silicon layer on the isolation
oxide sidewalls.  Details of the process are described below.
     STEP (1) Start with a wafer with p/n+ epi (25 microns).
      STEP (2) RIE isolation trenches with minimum-feature size and
space by using oxide/nitride mask layers.
 STEP (3) Fill the trenches with thermal/CVD oxide...