Browse Prior Art Database

Cut-Through Switch for Frame Relay Networks

IP.com Disclosure Number: IPCOM000099706D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 5 page(s) / 214K

Publishing Venue

IBM

Related People

Birman, A: AUTHOR

Abstract

Disclosed is a design for a high-speed n x n switch with cut-through (1) capability. In frame relay networks packets arriving simultaneously over different channels of the TDM input link could be intended for the same output channel. In the cut-through switch described here these packets are assembled and queued to the appropriate output channel within the operating cycle (one read cycle and one write cycle) of the common RAM unit used for storing packets. Variable length packets, a large number of input/output channels and a wide range of channel speeds can be accommodated.

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Cut-Through Switch for Frame Relay Networks

       Disclosed is a design for a high-speed n x n switch with
cut-through (1) capability. In frame relay networks packets arriving
simultaneously over different channels of the TDM input link could be
intended for the same output channel. In the cut-through switch
described here these packets are assembled and queued to the
appropriate output channel within the operating cycle (one read cycle
and one write cycle) of the common RAM unit used for storing packets.
Variable length packets, a large number of input/output channels and
a wide range of channel speeds can be accommodated.

      The figure illustrates the structure of the cut-through switch.
 The inputs to the switch are:
      Data/A, a data bus carrying bytes of incoming packets,
      Cha#/A, an address bus carrying the output channel
     number which is the destination of the incoming byte,
      Cha#/A, an address bus carrying the input channel
     number on which the incoming byte originated.

      The output is Data/D, an 8-bit data bus to the TDM output link
(data paths are assumed 8-bit wide, for simplicity of presentation).
Cha#/D the output channel number of the departing byte, is internally
generated by a signal synchronized with the TDM output link.

      The cut-through switch uses the techniques developed in (2,3)
for accessing pointer storage units (such as iCha/A, Cha/D, Cha/A)
and overlapping the updating of pointers with the read/write
operations.  The operation of the switch consists of 'arrivals
processing' and 'departures processing'. These operate simultaneously
and independently of each other.  "A" following a slash (as in
"Cha/A") refers to a field which is accessed by arrival processing
(similar conventions apply to "D" and "AD").

      DataBuf is a RAM unit which stores the packets. It is
partitioned into equal-size contiguous blocks called buffers.  Every
packet is stored in a buffer chain which consists of one or more
logically linked buffers. The buffers are dynamically allocated as in
(4).  The buffer chains associated with an output channel form a
channel queue.  Within every channel queue there is a buffer chain,
called the main chain, which plays a special role. It is created at
initialization time and is never terminated, bytes are read from it
for transmission on the output channel, it may contain bytes from
more than one packet, only packets in the main chain are candidates
for cut-through switching.

      Pointers are used to keep track of the data in DataBuf. A
pointer to the next byte to be read from DataBuf for transmission on
the output channel is called a read pointer and denoted by R.  A
pointer to the next free byte in a buffer chain to be used for
storing an incoming byte is called a write pointer denoted by W (see
[4] for details on the Pointer Update Logic).  When a buffer chain
stores a complete packet, a pointer to the first byt...